View AK4383_889099.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

asahi kasei [AK4383] ms0090-e-00 2001/4 - 1 - general description the AK4383 offers the perfect mix for cost and performance based audio systems. using akm's multi bit architecture for its modulator the AK4383 delivers a wide dynamic range while preserving linearity for improved thd+n performance. the AK4383 has full differential scf outputs, removing the need for ac coupling capacitors and increasing performance for systems with excessive clock jitter. the AK4383 accepts 192khz pcm data and 1-bit dsd data, ideal for a wide range of applications including dvd- audio and sacd. the AK4383 is offered in a space saving 20pin tssop package. features sampling rate ranging from 8khz to 192khz 24-bit 8 times fir digital filter on chip scf digital de-emphasis for 32k, 44.1k and 48khz sampling soft mute digital attenuator (linear 256 steps) pcm i/f format: 24-bit msb justified, 24/20/16-bit lsb justified or i 2 s master clock: 256fs, 384fs, 512fs or 768fs (pcm normal speed mode) 128fs, 192fs, 256fs or 384fs (pcm double speed mode) 128fs or 192fs (pcm quad speed mode) 512fs or 768fs (dsd mode) thd+n: -94db dynamic range: 110db dsd data input mode high tolerance to clock jitter power supply: 4.75 to 5.25v very small package: 20pin tssop (0.65mm pitch) ak4382 pin compatible lrck/dsdr bick/dclk sdti/dsdl pcm data interface mclk pdn s&h ? modulator aoutl+ 8x interpolator scf aoutr+ scf vdd vss de-emphasis control p interface clock divider csn cclk cdti dzfr s&h ? modulator 8x interpolator aoutl- aoutr- dzfl dsd data interface dclk dsdl dsdr dsdm 192khz 24-bit 2ch ? dac with dsd input AK4383
asahi kasei [AK4383] ms0090-e-00 2001/4 - 2 - ordering guide AK4383vt -40 +85 c 20pin tssop (0.65mm pitch) akd4383 evaluation board for AK4383 pin layout 1 mclk lrck/dsdr bick/dclk csn cclk cdti top view 2 3 4 5 6 7 8 dzfl dzfr vss vdd aoutl+ aoutl- aoutr+ aoutr- 20 19 18 17 16 15 14 13 pdn sdti/dsdl dclk dsdl 9 10 dsdm dsdr 12 11
asahi kasei [AK4383] ms0090-e-00 2001/4 - 3 - pin/function no. pin name i/o function 1 mclk i master clock input pin an external ttl clock should be input on this pin. 2 bick/dclk i audio serial data clock pin / dsd clock pin 3 sdti/dsdl i audio serial data input pin / dsd lch data input pin 4 lrck/dsdr i l/r clock pin / dsd rch data input pin 5 pdn i power-down mode pin when at ?l?, the AK4383 is in the power-down mode and is held in reset. the AK4383 should always be reset upon power-up. 6 csn i chip select pin 7 cclk i control data input pin 8 cdti i control data input pin in serial mode 9 dclk i dsd clock pin (pull-down pin) 10 dsdl i dsd lch data input pin (pull-down pin) 11 dsdr i dsd rch data input pin (pull-down pin) 12 dsdm i dsd mode enable pin (pull-down pin) ?0?: pcm data is input from pin 2-4. and the mode can be switched between pcm and dsd mode by register. ?1?: dsd data is input from pin 9-11. 13 aoutr- o rch negative analog output pin 14 aoutr+ o rch positive analog output pin 15 aoutl- o lch negative analog output pin 16 aoutl+ o lch positive analog output pin 17 vss - ground pin 18 vdd - power supply pin 19 dzfr o rch data zero input detect pin 20 dzfl o lch data zero input detect pin note: all input pins except pull-up pin should not be left floating.
asahi kasei [AK4383] ms0090-e-00 2001/4 - 4 - absolute maximum ratings (vss=0v; note 1) parameter symbol min max units power supply vdd -0.3 6.0 v input current (any pins except for supplies) iin - 10 ma input voltage vind -0.3 vdd+0.3 v ambient operating temperature ta -40 85 c storage temperature tstg -65 150 c note: 1. all voltages with respect to ground. warning: operation at or beyond these limits may results in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss=0v; note 1) parameter symbol min typ max units power supply vdd 4.75 5.0 5.25 v *akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [AK4383] ms0090-e-00 2001/4 - 5 - analog characteristics (ta=25 c; vdd=5.0v; fs=44.1khz; bick=64fs; signal frequency=1khz; 24bit input data; measurement frequency=20hz 20khz; r l 2k ? ; pcm mode; unless otherwise specified) parameter min typ max units resolution 24 bits dynamic characteristics (note 3) fs=44.1khz bw=20khz 0dbfs -60dbfs -94 -48 -87 - db db fs=96khz bw=40khz 0dbfs -60dbfs -92 -45 -84 - db db thd+n fs=192khz bw=40khz 0dbfs -60dbfs -92 -45 - - db db dynamic range (-60dbfs with a-weighted) (note 4) 102 110 db s/n (a-weighted) (note 5) 102 110 db interchannel isolation (1khz) 90 110 db interchannel gain mismatch 0.2 0.5 db dc accuracy gain drift 100 - ppm/ c output voltage (note 6) 2.3 2.5 2.7 vpp load resistance (note 7) 2 k ? power supplies power supply current (vdd) normal operation (pdn = ?h?, fs 96khz) normal operation (pdn = ?h?, fs=192khz) power-down mode (pdn = ?l?) (note 8) 20 25 10 34 42 100 ma ma a notes: 3. measured by audio precision (system two). refer to the evaluation board manual. 4. 100db at 16bit data. 5. s/n does not depend on input bit length. 6. full-scale voltage (0db). output voltage scales with the voltage of vref, aout (typ.@0db)=(aout+)-(aout-)= 2.5vpp vref/5. 7. for ac-load. 4k ? for dc-load. 8. all digital inputs including clock pins (mclk, bick and lrck) are held vdd or vss.
asahi kasei [AK4383] ms0090-e-00 2001/4 - 6 - sharp roll-off filter characteristics (ta = 25 c; vdd = 4.75 5.25v; fs = 44.1khz; dem = off; slow= ?0?; pcm mode) parameter symbol min typ max units digital filter passband 0.05db (note 9) -6.0db pb 0 - 22.05 20.0 - khz khz stopband (note 9) sb 24.1 khz passband ripple pr 0.02 db stopband attenuation sa 54 db group delay (note 10) gd - 19.3 - 1/fs digital filter + scf frequency response 20.0khz 40.0khz 80.0khz fs=44.1khz fs=96khz fs=192khz fr fr fr - - - 0.2 0.3 +0/-0.6 - - - db db db notes: 9. the passband and stopband frequencies scale with fs(system sampling rate). for example, pb=0.4535fs (@ 0.05db), sb=0.546fs. 10. the calculating delay time which occurred by digital filtering. this time is from setting the 16/24bit data of both channels to input register to the output of analog signal. slow roll-off filter characteristics (ta = 25 c; avdd, dvdd = 4.75~5.25v; fs = 44.1khz; dem = off; slow = ?1?; pcm mode) parameter symbol min typ max units digital filter passband 0.04db (note 11) -3.0db pb 0 - 18.2 8.1 - khz khz stopband (note 11) sb 39.2 khz passband ripple pr 0.005 db stopband attenuation sa 72 db group delay (note 10) gd - 19.3 - 1/fs digital filter + scf frequency response 20.0khz 40.0khz 80.0khz fs=44.khz fs=96khz fs=192khz fr fr fr - - - +0/-5 +0/-4 +0/-5 - - - db db db note: 11. the passband and stopband frequencies scale with fs. for example, pb = 0.185fs (@ 0.04db), sb = 0.888 fs. dc characteristics (ta=25 c; vdd=4.75 5.25v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.2 - - - - 0.8 v v high-level output voltage (iout=-80a) low-level output voltage (iout=80a) voh vol vdd-0.4 - -- 0.4 v v input leakage current (note 12) iin - - 10 a note: 12. dsdm, dclk, dsdl and dsdr pins have internal pull-down devices, nominally 100k ? .
asahi kasei [AK4383] ms0090-e-00 2001/4 - 7 - switching characteristics (ta = 25 c; vdd = 4.75 5.25v; c l = 20pf) parameter symbol min typ max units master clock frequency duty cycle fclk dclk 2.048 40 11.2896 36.864 60 mhz % lrck frequency normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 8 60 120 45 48 96 192 55 khz khz khz % pcm audio interface timing bick period normal speed mode double/quad speed mode bick pulse width low pulse width high bick ? ? to lrck edge (note 13) lrck edge to bick ? ? (note 13) sdti hold time sdti setup time tbck tbck tbckl tbckh tblr tlrb tsdh tsds 1/128fs 1/64fs 30 30 20 20 20 20 ns ns ns ns ns ns ns ns dsd audio interface timing dclk period dclk pulse width low pulse width high dclk edge to dsdl/r (note 14) tdck tdckl tdckh tddd 1/64fs 160 160 -20 20 ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn high time csn ? ? to cclk ? ? cclk ? ? to csn ? ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns reset timing pdn pulse width (note 15) tpd 150 ns notes: 13. bick rising edge must not occur at the same time as lrck edge. 14. dsd data transmitting device must meet this time. 15. the AK4383 can be reset by bringing pdn= ?l?.
asahi kasei [AK4383] ms0090-e-00 2001/4 - 8 - timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr audio serial interface timing (pcm mode) vih dclk vil tddd vih dsdl dsdr vil tdckh tdckl tdck audio serial interface timing (dsd normal mode, dckb = ?0?)
asahi kasei [AK4383] ms0090-e-00 2001/4 - 9 - vih dclk vil tddd vih dsdl dsdr vil tdckh tdckl tdck tddd audio serial interface timing (dsd phase modulation mode, dckb = ?0?) tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh write command input timing csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh write data input timing tpd vil pdn power-down timing
asahi kasei [AK4383] ms0090-e-00 2001/4 - 10 - operation overview d/a converion mode the AK4383 can perform d/a conversion for both pcm data and dsd data. when dsdm pin is ?h?, dsd data can be input from dclk, dsdl and dsdr pins. pcm data can be input from bick/dclk, sdti/dsdl and lrck/dsdr pins by setting dsdm pin to ?l?. in this case, bick/dclk, sdti/dsdl and lrck/dsdr pins can accept dsd data by enabling dsd mode via the register (d/p = ?1?). when pcm/dsd mode changes by dsdm pin or d/p bit, the AK4383 should be reset by pdn pin or rstn bit. (refer to d/a conversion mode switching timing.) dsdm pin d/p bit pin 2-4 pin 9-11 dac output 0 pcm * pcm l 1 dsd * dsd 0 * dsd dsd h 1 * dsd dsd table 1. dsd/pcm mode control(* don?t care.) system clock 1) pcm mode the external clocks, which are required to operate the AK4383, are mclk, lrck and bick. the master clock (mclk) should be synchronized with lrck but the phase is not critical. the mclk is used to operate the digital interpolation filter and the delta-sigma modulator. there are two methods to set mclk frequency. in manual setting mode (acks = ?0?: register 00h), the sampling speed is set by dfs0/1(table 2). the frequency of mclk at each sampling speed is set automatically. (table 3~5). in auto setting mode (acks = ?1?: default), as mclk frequency is detected automatically (table 6), and the internal master clock becomes the appropriate frequency (table 7), it is not necessary to set dfs0/1. all external clocks (mclk, bick and lrck) should always be present whenever the AK4383 is in the normal operation mode (pdn= ?h?). if these clocks are not provided, the AK4383 may draw excess current because the device utilizes dynamic refreshed logic internally. the AK4383 should be reset by pdn= ?l? after threse clocks are provided. if the external clocks are not present, the AK4383 should be in the power-down mode (pdn= ?l?). after exiting reset at power-up etc., the AK4383 is in the power-down mode until mclk is input. dfs1 dfs0 sampling rate (fs) 0 0 normal speed mode 8khz~48khz default 0 1 double speed mode 60khz~96khz 1 0 quad speed mode 120khz~192khz table 2. sampling speed (manual setting mode) lrck mclk bick fs 256fs 384fs 512fs 768fs 64fs 32.0khz 8.1920mhz 12.2880mhz 16.3840mhz 24.5760mhz 2.0480mhz 44.1khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 2.8224mhz 48.0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz 3.0720mhz table 3. system clock example (normal speed mode @manual setting mode)
asahi kasei [AK4383] ms0090-e-00 2001/4 - 11 - lrck mclk bick fs 128fs 192fs 256fs 384fs 64fs 88.2khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 5.6448mhz 96.0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz 6.1440mhz table 4. system clock example (double speed mode @manual setting mode) lrck mclk bick fs 128fs 192fs 64fs 176.4khz 22.5792mhz 33.8688mhz 11.2896mhz 192.0khz 24.5760mhz 36.8640mhz 12.2880mhz table 5. system clock example (quad speed mode @manual setting mode) mclk sampling speed 512fs 768fs normal 256fs 384fs double 128fs 192fs quad table 6. sampling speed (auto setting mode) lrck mclk (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs sampling speed 32.0khz - - - - 16.3840 24.5760 44.1khz - - - - 22.5792 33.8688 48.0khz - - - - 24.5760 36.8640 normal 88.2khz - - 22.5792 33.8688 - - 96.0khz - - 24.5760 36.8640 - - double 176.4khz 22.5792 33.8688 - - - - 192.0khz 24.5760 36.8640 - - - - quad table 7. system clock example (auto setting mode) 2) dsd mode the external clocks, which are required to operate the AK4383, are mclk and dclk. the master clock (mclk) should be synchronized with dsd clock (dclk) but the phase is not critical. the frequency of mclk is set by dcks bit. dcks 0 1 mclk 512fs 768fs dclk 64fs 64fs table 8. system clock (fs=44.1khz)
asahi kasei [AK4383] ms0090-e-00 2001/4 - 12 - audio serial interface format 1) pcm mode data is shifted in via the sdti pin using bick and lrck inputs. the dif0-2 as shown in table 7 can select five serial data modes. in all modes the serial data is msb-first, 2?s compliment format and is latched on the rising edge of bick. mode 2 can be used for 16/20 msb justified formats by zeroing the unused lsbs. mode dif2 dif1 dif0 sdti format bick figure 0 0 0 0 16bit lsb justified 32fs figure 1 1 0 0 1 20bit lsb justified 40fs figure 2 2 0 1 0 24bit msb justified 48fs figure 3 default 3 0 1 1 24bit i 2 s compatible 48fs figure 4 4 1 0 0 24bit lsb justified 48fs figure 2 table 9. audio data formats sdti bick lrck sdti 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3210 1514 ( 32fs ) ( 64fs ) 014 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 don?t care don?t care 15:msb, 0:lsb mode 0 15 14 6 5 4 3 2 1 0 lch data rch data figure 1. mode 0 timing sdti lrck bick ( 64fs ) 09 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 mode 1 don?t care don?t care 19:msb, 0:lsb sdti mode 4 23:msb, 0:lsb 20 19 0 20 19 0 don?t care don?t care 22 21 22 21 lch data rch data 8 23 23 8 figure 2. mode 1,4 timing
asahi kasei [AK4383] ms0090-e-00 2001/4 - 13 - lrck bick ( 64fs ) sdti 022 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 30 22 224 23 30 22 1 0 don?t care 23 22 23 figure 3. mode 2 timing lrck bick ( 64fs ) sdti 03 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 25 3 224 23 25 22 1 0 don?t care 23 23 figure 4. mode 3 timing 2) dsd mode in case of dsd mode, dif0-2 are ignored. the frequency of dclk is fixed to 64fs. dckb bit can invert the polarity of dclk. dclk (64fs) dckb=1 dclk (64fs) dckb=0 dsdl,dsdr normal dsdl,dsdr phase modulation d1 d0 d1 d2 d0 d2 d3 d1 d2 d3 figure 5. dsd mode timing
asahi kasei [AK4383] ms0090-e-00 2001/4 - 14 - de-emphasis filter a digital de-emphasis filter is available for 32, 44.1 or 48khz sampling rates (tc = 50/15s) and is enabled or disabled with dem0 and dem1. in case of double speed and quad speed mode, the digital de-emphasis filter is always off. dem1 dem0 mode 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 8. de-emphasis filter control (normal speed mode) output volume the AK4383 includes channel independent digital output volumes (att) with 256 levels at linear step including mute. these volumes are in front of the dac and can attenuate the input data from 0db to ?48db and mute. when changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. table 11 shows transition times of 1 level and 256 levels. the setting value of the register is held when switching between pcm mode and dsd mode. the transition time at dsd mode is the same as normal speed mode. transition time sampling speed 1 level 255 to 0 normal speed mode 4lrck 1020lrck double speed mode 8lrck 2040lrck quad speed mode 16lrck 4080lrck table 11. att transition time zero detection the AK4383 has channel-independent zeros detect function. when the input data at each channel is continuously zeros for 8192 lrck cycles, dzf pin of each channel goes to ?h?. dzf pin of each channel immediately goes to ?l? if input data of each channel is not zero after going dzf ?h?. if rstn bit is ?0?, dzf pins of both channels go to ?h?. dzf pins of both channels go to ?l? at 2~3/fs after rstn bit returns to ?1?. if dzfm bit is set to ?1?, dzf pins of both channels go to ?h? only when the input data at both channels are continuously zeros for 8192 lrck cycles. zero detect function can be disabled by dzfe bit. in this case, dzf pins of both channels are always ?l?. dzfb bit can invert the polarity of dzf pin.
asahi kasei [AK4383] ms0090-e-00 2001/4 - 15 - soft mute operation soft mute operation is performed at digital domain. when the smute bit goes to ?1?, the output signal is attenuated by - during att_data att transition time (table 11) from the current att level. when the smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the att level during att_data att transition time. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. smute bit attenuation dzf pin att level - aout 8192/fs gd gd (1) (2) (3) (4) (1) notes: (1) att_data att transition time (table 11). for example, in normal speed mode, this time is 1020lrck cycles (1020/fs) at att_data=255. (2) the analog output corresponding to the digital input has a group delay, gd. (3) if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. (4) when the input data at each channel is continuously zeros for 8192 lrck cycles, dzf pin of each channel goes to ?h?. dzf pin immediately goes to ?l? if input data are not zero after going dzf ?h?. figure 6. soft mute and zero detection
asahi kasei [AK4383] ms0090-e-00 2001/4 - 16 - system reset the AK4383 should be reset once by bringing pdn= ?l? upon power-up. the analog section exits power-down mode by mclk input and then the digital section exits power-down mode after the internal counter counts mclk during 4/fs. power-down the AK4383 is placed in the power-down mode by bringing pdn pin ?l? and the anlog outputs are floating (hi-z). figure 7 shows an example of the system timing at the power-down and power-up. normal operation internal state pdn power-down normal operation gd gd ?0? data d/a out (analog) d/a in (digital) clock in mclk, lrck, bick (1) (3) (6) dzfl/dzfr external mute (5) (3) (1) mute on (2) (4) don?t care notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs are floating (hi -z) at the power-down mode. (3) click noise occurs at the edge of pdn signal. this noise is output even if ?0? data is input. (4) the external clocks (mclk, bick and lrck) can be stopped in the power-down mode (pdn = ?l?). (5) please mute the analog output externally if the click noise (3) influences system application. the timing example is shown in this figure. (6) dzf pins are ?l? in the power-down mode (pdn = ?l?). figure 7. power-down/up sequence example
asahi kasei [AK4383] ms0090-e-00 2001/4 - 17 - reset function when rstn=0, dac is powered down but the internal register values are not initialized. the analog outputs go to vcom voltage and dzfl/dzfr pins go to ?h?. figure 8 shows the example of reset by rstn bit. internal state rstn bit digital block power-down normal operation gd gd ?0? data d/a out (analog) d/a in (digital) clock in mclk,lrck,bick (1) (3) dzf (3) (1) (2) normal operation 2/fs(5) internal rstn bit 2~3/fs (6) 3~4/fs (6) don?t care (4) notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs go to vcom voltage. (3) click noise occurs at the edges(? ?) of the internal timing of rstn bit. this noise is output even if ?0? data is input. (4) the external clocks (mclk, bick and lrck) can be stopped in the reset mode (rstn = ?l?). (5) dzf pins go to ?h? when the rstn bit becomes ?0?, and go to ?l? at 2/fs after rstn bit becomes ?1?. (6) there is a delay, 3~4/fs from rstn bit ?0? to the internal rstn bit ?0?, and 2~3/fs from rstn bit ?1? to the internal rstn ?1?. figure 8. reset sequence example
asahi kasei [AK4383] ms0090-e-00 2001/4 - 18 - d/a conversion mode switching timing rstn bit d/a data d/a mode 4/fs 0 pcm data dsd data pcm mode dsd mode figure 9. d/a mode switching timing (pcm to dsd) rstn bit d/a data d/a mode 4/fs dsd data pcm data dsd mode pcm mode figure 10. d/a mode switching mode timing (dsd to pcm) caution: in dsd mode, the signal level is ranging from 25% to 75%. peak levels of dsd signal above this duty are not recommended by sacd format book (scarlet book).
asahi kasei [AK4383] ms0090-e-00 2001/4 - 19 - mode control interface internal registers may be written by 3-wire p interface pins, csn, cclk and cdti. the data on this interface consists of chip address (2bits, c1/0; fixed to ?01?), read/write (1bit; fixed to ?1?, write only), register address (msb first, 5bits) and control data (msb first, 8bits). the AK4383 latches the data on the rising edge of cclk, so data should clocked in on the falling edge. the writing of data becomes valid by csn ? ?. the clock speed of cclk is 5mhz (max). the csn and cclk must be fixed to ?h? when the register does not be accessed. pdn = ?l? resets the registers to their default values. the internal timing circuit is reset by rstn bit, but the registers are not initialized. cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 c1-c0: chip address (fixed to ?01?) r/w: read/write (fixed to ?1?, write only) a4-a0: register address d7-d0: control data figure 11. control i/f timing *the AK4383 does not support the read command and chip address. c1/0 and r/w are fixed to ?011? *when the AK4383 is in the power down mode (pdn = ?l?) or the mclk is not provided, writing into the control register is inhibited. register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks 0 0 dif2 dif1 dif0 pw rstn 01h control 2 dzfe dzfm slow dfs1 dfs0 dem1 dem0 smute 02h control 3 0 0 dcks d/p dckb dzfb 0 0 03h lch att att7 att6 att5 att4 att3 att2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 att0 notes: for addresses from 05h to 1fh, data must not be written. when pdn pin goes ?l?, the registers are initialized to their default values. when rstn bit goes ?0?, the only internal timing is reset and the registers are not initialized to their default values. all data can be written to the register even if pw or rstn bit is ?0?.
asahi kasei [AK4383] ms0090-e-00 2001/4 - 20 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 acks 0 0 dif2 dif1 dif0 pw rstn default 1 0 0 0 1 0 1 1 rstn: internal timing reset control 0: reset. all registers are not initialized. 1: normal operation when mclk frequency or dfs changes, the AK4383 should be reset by pdn pin or rstn bit. pw: power down control 0: power down. all registers are not initialized. 1: normal operation dif2-0: audio data interface formats (see table 9, pcm only) initial: ?010?, mode 3 acks: master clock frequency auto setting mode enable (pcm only) 0: disable, manual setting mode 1: enable, auto setting mode master clock frequency is detected automatically at acks bit ?1?. in this case, the setting of dfs1-0 are ignored. when this bit is ?0?, dfs1-0 set the sampling speed mode. addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 dzfe dzfm slow dfs1 dfs0 dem1 dem0 smute default 0 0 0 0 0 0 1 0 smute: soft mute enable 0: normal operation 1: dac outputs soft-muted dem1-0: de-emphasis response (see table 10, pcm only) initial: ?01?, off dfs1-0: sampling speed control (pcm only) 00: normal speed mode 01: double speed mode 10: quad speed mode when changing between normal/double speed mode and quad speed mode, some click noise occurs. slow: slow roll-off filter enable (pcm only) 0: sharp roll-off filter 1: slow roll-off filter dzfe: data zero detect enable 0: disable 1: enable zero detect function can be disabled by dzfe bit ?0?. in this case, the dzf pins of both channels are always ?l?.
asahi kasei [AK4383] ms0090-e-00 2001/4 - 21 - dzfm: data zero detect mode 0: channel separated mode 1: channel anded mode if the dzfm bit is set to ?1?, the dzf pins of both channels go to ?h? only when the input data at both channels are continuously zeros for 8192 lrck cycles. addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h control 3 0 0 dcks d/p dckb dzfb 0 0 default 0 0 0 0 0 0 0 0 dzfb: inverting enable of dzf 0: dzf goes ?h? at zero detection 1: dzf goes ?l? at zero detection dckb: polarity of dclk (dsd only) 0: dsd data is output from dclk falling edge 1: dsd data is output from dclk rising edge d/p: dsd/pcm mode select 0: pcm mode. sclk, sdti, lrck input on pin 2-4. 1: dsd mode. dclk, dsdl, dsdr input on pin 2-4. when d/p changes, the AK4383 should be reset by pdn pin or rstn bit. dcks: master clock frequency select at dsd mode (dsd only) 0: 512fs 1: 768fs addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h lch att att7 att6 att5 att4 att3 att2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 att0 default 1 1 1 1 1 1 1 1 att = 20 log (att_data / 255) [db] 00h: mute
asahi kasei [AK4383] ms0090-e-00 2001/4 - 22 - system design figure 12 shows the system connection diagram. an evaluation board (akd4383) is available in order to allow an easy study on the layout of a surrounding circuit. mclk 1 bick/dclk 2 sdti/dsdl 3 lrck/dsdr 4 pdn 5 csn 6 cclk 7 cdti 8 dzfl 20 dzfr 19 vdd 18 vss 17 aoutl+ 16 aoutl- 15 aoutr+ 14 aoutr- 13 micro- controller AK4383 reset & power down 10u 0.1u + lch lpf rch lpf rch out lch out analog ground digital ground lch mute rch mute analog supply 5v dclk 9 dsdl 10 dsdm 12 dsdr 11 pcm/dsd data controller dsd data controller master clock figure 12. typical connection diagram notes: - lrck = fs, bick = 64fs. - when aout drives some capacitive load, some resistor should be added in series between aout and capacitive load. - all input pins except pull-down pins should not be left floating. 1. grounding and power supply decoupling vdd and vss are supplied from analog supply and should be separated from system digital supply. decoupling capacitor, especially 0.1 f ceramic capacitor for high frequency should be placed as near to vdd as possible. the differential voltage between vdd and vss pins set the analog output range. 2. analog outputs the analog outputs are full-differential outputs and 0.5 x vdd vpp (typ) centered around the internal common voltage (about avdd/2). the differential outputs are summed externally, v aout =(aout+)-(aout-) between aout+ and aout-. if the summing gain is 1, the output range is 5.0vpp (typ @vdd=5v). the bias voltage of the external summing circuit is supplied externally. the input data format is 2?s complement. the output voltage (v aout ) is a positive full scale for 7fffff (@24bit) and a negative full scale for 800000h (@24bit). the ideal v aout is 0v for 000000h (@24bit). the internal switched-capacitor filter and external low pass filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. dc offset on aout+/- is eliminated without ac coupling since the analog outputs are differential.
asahi kasei [AK4383] ms0090-e-00 2001/4 - 23 - 3. external analog filter it is recommended by sacd format book (scarlet book) that the filter response at sacd playback is an analog low pass filter with a cut-off frequency of maximum 50khz and a slop of minimum 30db/oct. the AK4383 can achieve this filter response by combination of the internal filter (table 12) and an external filter (figure 11). frequency gain 20khz -0.4db 50khz -2.8db 100khz -15.5db table 12. internal filter response at dsd mode 1.8k 4.3k 1.0k 1.8k 1.0k 4.3 k 270p +vop 270p -vo p aout- aout+ 3300p analog out 2.0k 2.0k 47u 47u 2200p - + 2.5vpp 5.65vpp 2.5vpp figure 13. external 3rd order lpf circuit example frequency gain 20khz -0.05dbr 50khz -0.51dbr 100khz -16.8dbr dc gain = 1.07db table 13. 3rd order lpf (figure 13) response application example 1) connection with dsd decoder, cxd2751q bckd dsal mcki cxd2751q 22.579m /33.868m dclk mclk AK4383 dsar dsdl dsdr dsdm phase modulation mode
asahi kasei [AK4383] ms0090-e-00 2001/4 - 24 - package 0.1 0.1 0 10 detail a seating plane 0.10 0.17 0.05 0.22 0.1 0.65 6.5 1.10max a 1 10 11 20 20 p in tssop ( unit: mm ) 4.4 6.4 0.2 0.5 0.2 package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate
asahi kasei [AK4383] ms0090-e-00 2001/4 - 25 - marking akm 4383vt xxyyy 1) asahi kasei logo 2) marketing code : 4383vt 3) date code : xxyyy (5 digits) xx: lot# yyy: date code 4) pin #1 indication important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

▲Up To Search▲

Price & Availability of AK4383

	To Download AK4383 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .